Saturday, March 06, 2004
What's the difference between uncached memory and cached memory?
On the StrongARM, Windows CE maps each of the memory ranges specified in the OEMAddressTable to two different virtual addresses, on between 0x80000000 and 0x9FFFFFFF and the second between 0xA0000000 and 0xBFFFFFFF. The first range is configured in the page tables with the Cacheable and Bufferable bits. Reads and writes for these ranges pass through the StrongARM's 8 Kbyte data cache. These virtual addresses are typically used for RAM read/writes and ROM reads because of the performance gained. The second range is mapped in the page tables with the Cacheable and Bufferable bits off, so accesses within this range do not use the StrongARM's dcache. These addresses are intended for use when performing I/O or other operations where caching is not appropriate.
The StrongARM's main dcache is organized as 256 lines of 8 32-bit words and is 32-way set associative. A memory read into a cached region that misses (i.e. not already stored in) the cache causes an 8-word cache line fill into the cache. Subsequent reads that hit the cache are delivered out of the cache and do not require further accesses to the physical memory and are MUCH faster. Similarly, writes that hit the cache are stored into the cache and mark the cache line as dirty. Once all 32-ways of the cache are allocated, the next cache read miss causes the first way to be replaced (copying it back to memory first if it was marked dirty).
The StrongARM's main dcache is organized as 256 lines of 8 32-bit words and is 32-way set associative. A memory read into a cached region that misses (i.e. not already stored in) the cache causes an 8-word cache line fill into the cache. Subsequent reads that hit the cache are delivered out of the cache and do not require further accesses to the physical memory and are MUCH faster. Similarly, writes that hit the cache are stored into the cache and mark the cache line as dirty. Once all 32-ways of the cache are allocated, the next cache read miss causes the first way to be replaced (copying it back to memory first if it was marked dirty).
